This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-150254, filed May 22, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a sync signal generating circuit provided in a semiconductor integrated circuit such as a synchronous DRAM. More particularly, this invention relates to a sync signal generating circuit for generating an internal clock signal from an external clock signal, which internal clock signal is synchronized with the external clock signal.
In modern semiconductor integrated circuits, there is a demand for a higher input/output operation speed in an I/O section (data input/output section). In order to make the phase of data agree with that of a system clock signal, a PLL (Phase Locked Loop) or a DLL (Delay Locked Loop) is used. Among DLLs, a mirror-type DLL is more advantageous than a feedback-type DLL since the former has a high synchronization speed.
In particular, in an ASMD (Analog Synchronous Mirror Delay) disclosed in the Journal of Solid-State Circuit, Vol. 34, No. 4, April, 1999, xe2x80x9cAn Analog Synchronous Mirror Delay for High-Speed DRAM Applicationxe2x80x9d, or an analog-operable mirror-type DLL disclosed in Japanese Patent Application No. 11-228710, no such quantization error, as occurs in a digital-operable mirror-type DLL, will occur and high-precision operational characteristics can be obtained.
FIG. 1 shows an example of a conventional analog-operable mirror-type DLL. The DLL comprises an input buffer 51, an I/O replica 52, a comparator replica 53, two ramp-voltage generating circuits (RVG1, RVG2) 54 and 55, a comparator 56, and a DQ buffer 57.
The input buffer 51 receives an external clock signal and outputs a clock signal CLK1 obtained by delaying the external clock signal. The I/O replica 52 receives the clock signal CLK1 and outputs a clock signal CLK2, which is obtained by delaying the clock signal CLK1 by a delay time substantially equal to a sum of a delay time in the input buffer 51 and a delay time in the DQ buffer 57 from a time point of change of an internal clock signal to a time point of outputting of DQ. The comparator replica 53 receives the clock signal CLK2 and outputs a clock signal obtained by delaying the clock signal CLK2 by a delay time substantially equal to a delay time in the comparator 56.
The ramp-voltage generating circuit, RVG154, receives the clock signal from the comparator replica 53 and the clock signal CLK1 and outputs a ramp voltage (analog voltage) Vmeans. The potential level of the ramp voltage Vmeans rises at a constant gradient in synchronism with the rising of the clock signal from the comparator replica 53, and the rising of this potential level stops in synchronism with the rising of the clock signal CLK1.
The ramp-voltage generating circuit, RVG255, receives the clock signal CLK1 and outputs a ramp voltage (analog voltage) Vdly, whose potential level rises at a constant gradient in synchronism with the rising of the clock signal CLK1. Assume that the gradients of the rising of the output voltages Vmeans and Vdly in both ramp-voltage generating circuits 54 and 55 are equal.
The comparator 56 compares both voltages Vmeans and Vdly and produces an internal clock signal on the basis of the comparison result. The DQ buffer 57 receives internal data and the internal clock signal, takes in the internal data in synchronism with the internal clock signal, and outputs the data as data DQ to the outside.
FIG. 2 is a signal waveform diagram illustrating an example of the operation of the DLL shown in FIG. 1.
If the external clock signal is supplied, the clock signal CLK1 rises with a delay tIB (input buffer delay: a delay time in the input buffer 51) relative to the external clock signal. Then, the clock signal CLK2 rises with a delay tREP (=tIB+tOB: tOB is a delay time in the DQ buffer 57) relative to the clock signal CLK1. After a delay time in the comparator replica 53 from the rising of the clock signal CLK2, the output clock signal of the comparator replica 53 rises and the output voltage Vmeans in the ramp-voltage generating circuit 54 begins to rise.
If a second-cycle external clock signal rises after the lapse of a first cycle time tCLK of the external clock signal, and a second-cycle clock signal CLK1 rises, the rising of the output voltage Vmeans of the ramp-voltage generating circuit 54 stops and, in turn, the output voltage Vdly of the other ramp-voltage generating circuit 55 begins to rise. The voltages Vdly and Vmeans are compared and, when both voltages have coincided, the internal clock signal rises. The data DQ is output from the DQ buffer 57 with a delay tOB (DQ buffer delay) relative to the rising of the internal clock signal.
Since the output voltages Vmeans and Vdly of the two ramp-voltage generating circuits 54 and 55 rise at the same gradient, a time period tRAMP from when the output voltage Vmeans of the ramp voltage generating circuit 54 begins to rise to when the rising of the output voltage Vmeans stops in synchronism with the clock signal CLK1 is equal to a time period tRAMP from when the output voltage Vdly of the other ramp-voltage generating circuit 55 begins to rise to when the output voltage Vdly becomes equal to the output voltage Vmeans. In addition, the delay time of the comparator replica 53 is substantially equal to that of the comparator 56. Thus, assuming that each delay time is tCMP, a delay time xcex94TOTAL of the data DQ relative to the external clock signal is given by
xcex94TOTAL=tIB+tREP+tCMP+tRAMP+tRAMP+tCMP+tOBxe2x80x83xe2x80x83(1)
Since tIB+tOB=tREP, it this is substited in equation (1), the following equation (2) is obtained:
xcex94TOTAL=2(tREP+tCMP+tRAMP)xe2x80x83xe2x80x83(2)
The time period tRAMP is given by the following equation (3), that is, by subtracting the sum of tIB, tREP and tCMP from the time period (tIB+tCLK) from the timing at which the first-cycle external clock signal rises to the timing at which the second-cycle clock signal CLK1 rises:                                                         tRAMP              =                              xe2x80x83                            ⁢                                                (                                      tIB                    +                    tCLK                                    )                                -                                  (                                      tIB                    +                    tREP                    +                    tCMP                                    )                                                                                                        =                              xe2x80x83                            ⁢                              tCLK                -                                  (                                      tREP                    +                    tCMP                                    )                                                                                        (        3        )            
If equation (3) is substituted in equation (2), equation (4) is obtained:                                                                         Δ                ⁢                                  xe2x80x83                                ⁢                TOTAL                            =                              xe2x80x83                            ⁢                              2                ⁢                                  {                                      tREP                    +                    tCMP                    +                    tCLK                    -                                          (                                              tREP                        +                        tCMP                                            )                                                        }                                                                                                        =                              xe2x80x83                            ⁢                              2                ⁢                                  xe2x80x83                                ⁢                tCLK                                                                        (        4        )            
In other words, the data DQ, synchronized with the external clock signal, is output from the third-cycle external clock signal.
The comparator 56 shown in FIG. 1 may be, for example, a dynamic-type comparator using a differential amplifier, a capacitor and inverters composed of NMOSFETs and PMOSFETs.
The comparator, such as a dynamic-type comparator using a differential amplifier, a capacitor and inverters, is an analog circuit. In general terms, there arises a variance in characteristics of an analog circuit due to a fabrication process, a voltage used and a temperature in operation (hereinafter referred to as xe2x80x9cPVTxe2x80x9d (i.e. Process, Voltage and Temperature)). In particular, if a digital-specific process is applied to circuit integration, a greater process variance will occur, compared to the case of using an analog-specific process. Such a PVT variance adversely affects, in particular, analog circuits and it causes a variance in characteristics.
FIG. 3 shows a delay time variation (ps) occurring when the threshold voltages (Vth) of the NMOSFETs and PMOSFETs of the dynamic-type comparator are higher (xe2x80x9cHighxe2x80x9d) or lower (xe2x80x9cLowxe2x80x9d) than a specified value (xe2x80x9ccenterxe2x80x9d) and when the temperature (Temp.(xc2x0 C.)) varies in a range between xe2x88x9210xc2x0 C. and 100xc2x0 C. When both the threshold voltages (Vth) of the NMOSFETs and PMOSFETs of the dynamic-type comparator are higher than the specified value (xe2x80x9cHigh/Highxe2x80x9d), the delay time greatly increases. On the other hand, when both the threshold voltages (Vth) of the NMOSFETs and PMOSFETs of the dynamic-type comparator are lower than the specified value (xe2x80x9cLow/Lowxe2x80x9d), the delay time greatly decreases. In addition, the lower the temperature, the greater the delay time.
As described above, there is a PVT variance in the comparator 56 shown in FIG. 1, which is composed of an analog circuit, and the PVT variance varies the delay time tCMP of the comparator 56. Then, the phase of the internal clock signal output from the comparator 56 will be displaced. As a result, as shown in FIG. 4, the data window (i.e. a time period for data output) of the DQ buffer 57, which takes in data in synchronism with the internal clock signal, will be displaced and the output data DQ will not be synchronized with the external clock signal.
The amount of the delay time variation in the comparator is basically a variation amount which cannot be compensated. Even if a compensating circuit is to be fabricated, it is very difficult to compose such a circuit with a digital circuit structure.
As has been described above, the conventional analog-operable mirror-type DLL is free of such a quantization error, as occurs in a digital-operable mirror-type DLL, and can possess high-precision operational characteristics. However, since the analog-operable mirror-type DLL is an analog circuit, the delay time thereof will vary due to a fabrication process, voltage used and temperature in operation, and high-precision sync characteristics cannot be obtained.
The present invention has been made in consideration of the above problem, and its object is to provide an analog-operable sync signal generating circuit which can have high-precision sync characteristics.
In order to achieve the object, according to an aspect of the invention, there is provided a sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a variable delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit and delivering a delayed output; a first voltage generating circuit, connected to the variable delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the variable delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages and outputting an internal clock signal; an internal circuit connected to the voltage comparing circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a second delay circuit, connected to the voltage comparing circuit, for delaying the internal clock signal by a second time period that is substantially equal to the first time period, and delivering a delayed output; and a phase comparator, connected to the second delay circuit and the input buffer circuit, for comparing phases of outputs of the second delay circuit and the input buffer circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs, wherein a delay time in the variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.
According to another aspect of the invention, there is provided a sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a variable delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit and delivering a delayed output; a first voltage generating circuit, connected to the variable delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the variable delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages and outputting an internal clock signal; an internal circuit connected to the voltage comparing circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a first frequency-division circuit, connected to the voltage comparing circuit, for frequency-dividing the internal clock signal and delivering a frequency-division output; a second delay circuit, connected to the first frequency-division circuit, for delaying the output of the first frequency-division circuit by a second time period that is substantially equal to the first time period, and delivering a delayed output; a second frequency-division circuit, connected to the input buffer circuit, for frequency-dividing the output of the input buffer circuit and delivering a frequency-division output; and a phase comparator, connected to the second delay circuit, the second frequency-division circuit and the variable delay circuit, for comparing phases of outputs of the second delay circuit and the second frequency-division circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs to the variable delay circuit, wherein a delay time in the variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.
According to still another aspect of the invention, there is provided a sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a second delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit by a second time period and delivering a delayed output; a first voltage generating circuit, connected to the second delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the second delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing/variable delay circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages, outputting an internal clock signal, delaying the internal clock signal, and delivering a delayed output; an internal circuit connected to the voltage comparing/variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a third delay circuit, connected to the voltage comparing/variable delay circuit, for delaying the internal clock signal by a time period that is substantially equal to the first time period, and delivering a delayed output; and a phase comparator, connected to the third delay circuit and the input buffer circuit, for comparing phases of outputs of the third delay circuit and the input buffer circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs, wherein a delay time in the voltage comparing/variable delay circuit is adjusted on the basis of the control signal corresponding to the phase difference, which is output from the phase comparator.
According to still another aspect of the invention, there is provided a sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a second delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit by a second time period and delivering a delayed output; a first voltage generating circuit, connected to the second delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the second delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing/variable delay circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages, outputting an internal clock signal, delaying the internal clock signal, and delivering a delayed output; an internal circuit connected to the voltage comparing/variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a first frequency-division circuit, connected to the voltage comparing/variable delay circuit, for frequency-dividing the internal clock signal and delivering a frequency-division output; a third delay circuit, connected to the first frequency-division circuit, for delaying the output of the first frequency-division circuit by a third time period that is substantially equal to the first time period, and delivering a delayed output; a second frequency-division circuit, connected to the input buffer circuit, for frequency-dividing the output of the input buffer circuit and delivering a frequency-division output; and a phase comparator, connected to the third delay circuit, the second frequency-division circuit and the voltage comparing/variable delay circuit, for comparing phases of outputs of the third delay circuit and the second frequency-division circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs to the voltage comparing/variable delay circuit, wherein a delay time in the voltage comparing/variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.
According to still another aspect of the invention, there is provided a sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a second delay circuit, connected to the first delay circuit and the input buffer circuit, for starting delaying of the output of the first delay circuit at a time of transition of a level of the output of the first delay circuit and stopping the delaying of the output of the first delay circuit at a time of transition of a level of the output of the input buffer circuit; a third delay circuit, connected to the input buffer circuit, for starting delaying of the output of the input buffer circuit at a time of transition of a level of the output of the input buffer circuit, delaying the output of the input buffer circuit by a delay time substantially equal to a delay time in the second delay circuit, and outputting a delayed output; a variable delay circuit, connected to the third delay circuit, for delaying the output of the third delay circuit and outputting an internal clock signal; an internal circuit connected to the variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a fourth delay circuit, connected to the variable delay circuit, for delaying the internal clock signal by a time period that is substantially equal to the first time period, and delivering a delayed output; and a phase comparator, connected to the fourth delay circuit and the input buffer circuit, for comparing phases of outputs of the fourth delay circuit and the input buffer circuit, and outputting to the variable delay circuit a control signal corresponding to a phase difference obtained by the comparison of the outputs, wherein a delay time in the variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.